Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 547

Setting Miscellaneous Bits
This sequence is used in most following programming models as interme-
diate step.
Set the required values for:
•
IDP_SMODEx
format for the serial inputs (left-justified I
mode).
•
IDP_Pxx_PDAPMASK
input mask, if the PDAP is used.
•
IDP_PP_SELECT
the DAI pins or the
•
IDP_PDAP_CLKEDGE
if data is latched on the rising or falling clock edge, if the PDAP is
used.
Starting Core Interrupt-Driven Transfer
To start a core interrupt-driven data transfer:
1. Clear the FIFO by setting (= 1)
IDP_CTL1
2. Keep the
nected to low, by setting the proper values in the SRU registers.
3. Refer to
4. Program the SRU registers to establish the proper connection to
the SIP and/or PDAP being used. Keep the unused clock and frame
sync signals connected to low.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bits in the
IDP_CTLx
bits in the
bits in the
IDP_PP_CTL
pins, if the PDAP is used.
DATA
bit (bit 29) in the
register).
and frame sync inputs of the SIP and PDAP con-
SCLK
"Setting Miscellaneous Bits"
register to specify the frame sync
2
S, or right-justified
register to specify the
IDP_PP_CTL
register to specify input from
IDP_PP_CTL
bit (bit 31 in the
IDP_FFCLR
above.
Input Data Port
register to specify
11-27