Functional Description - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

FIR Accelerator

Functional Description

Figure 6-3 shows the block diagram of the 1024-TAP FIR hardware accel-
erator. The accelerator consists of a 1024 word coefficient memory, a
1024 deep delay line for data, and four MAC units. The accelerator runs
at the peripheral clock frequency (
FIR CONTROL
REGISTERS
C
O
E
F
F
I
.
C
I .
E
.
N
T
1024 x 32
S
Figure 6-3. FIR Block Diagram
The FIR accelerator has following logical sub blocks.
1. A data path unit that consists of:
a. A 1024 deep coefficient memory
b. A 1024 deep delay line for the data
6-30
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PCLK
CORE PMD/DMD
BUS
FIR CONTROLLER
OUTPUT
REGISTER
FIR
COEFF
COMPUTE
ACCESS
UNIT
CONTROL
(4 MACs)
PARTIAL SUM
REGISTER
ADSP-214xx SHARC Processor Hardware Reference
).
IOD0
BUS
DMA
CONTROLLER
DATA
ACCESS
CONTROL
1024 x 32
PREFETCH
BUFFER
D
E
L
A
Y
.
.
L
I
.
N
E