Table of Contents
Advertisement
Features
Table 15-1. SPI Port Specifications (Cont'd)
Feature
Transmission Full Duplex
Access Type
Data Buffer
Core Data Access
DMA Data Access
DMA Channels
DMA Chaining
Interrupt Source
Boot Capable
Local Memory
Clock Operation
Features
The processor's SPI ports provide the following features and capabilities.
• A simple 4-wire interface consisting of two data pins, a device
select pin, and a clock pin.
• Special data formats to accommodate little and big endian data,
different word lengths, and packing modes.
• Master and multiples slave (multi devices) in which the
ADSP-214xx master processor can be connected to up to four
other SPI devices.
• Parallel core and DMA access allow full duplex operation.
• Open drain outputs to avoid data contention and to support
multimaster scenarios.
15-2
www.BDTIC.com/ADI
SPI/SPIB
Yes (Core and DMA)
Yes
Yes
Yes
1
Yes
Core/DMA
Yes
No
f
PCLK
ADSP-214xx SHARC Processor Hardware Reference
/4 (slave) f
/8 (master)
PCLK
Advertisement
Chapters
Table of Contents
