Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 243

Table of Contents

INTERNAL MEMORY

SAMPLE (N-M)

DMA DESTINATION

(SAMPLES FETCHED

FROM D-LINE)

Figure 3-28. Delay Line DMA Reads

these delay line reads. Once the read count completes, the

final tap. Finally, the delay line DMA access completes and the

DMA completion interrupt is generated. If chaining is enabled, the

interrupt is dependent on the

can only be initialized using the TCB. In order to use the delay line

DMA for a single DMA sequence, initialize the

zero in the TCB.

For each 32-bit tap read, the external read index is shown in

Note that one tap list entry starts multiple reads.

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

EXTERNAL MEMORY

are zero) for the

bit setting. The delay line DMA

External Port

(DELAY LINE)

Chapters

Table of Contents