Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 807

Running Reset
Using the SPI protocol with additional control words and commands,
running reset can become an addition command from the host or from the
processor as described in the following procedure.
1. The host initiates a running reset by informing the processor over
the command interface.
2. The processor receives the command and completes any unfinished
work which may also include writing to the
3. Wait at least 5
input.
4. When the processor is ready to accept the running reset, it signals
the host over the command interface.
5. The host drives the running reset input into the processor.
Running The Boot Kernel
The following sections provide information on the use of the boot kernal
with the SHARC processors.
Loading the Boot Kernel Using DMA
1. At reset, the processor is hardwired (using the boot configuration
pins) to load 256 x 48-bit instruction words via a DMA starting at
IVT_START_ADDRESS
2. The sequencer is put into IDLE until the boot interrupt occurs.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
cycles to ensure that the pin is configured as an
CCLK
.
System Design
register.
RUNRSTCTL
23-25