Clocking; Master Clock - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Clocking

operation mode, refer to
Modes" on page
Serial Port Error Registers (SPERRxx). Two error registers (
/
RCTLx SPERRSTAT
transfers. Detected errors can be frame sync violation or buffer
over/underflow conditions. For more information, see
on page 10-51 and
Multichannel Control Registers (SPMCTLx). There is one global control
and status register for each SPORT (SPORT7–0) for multichannel opera-
tion. These registers define the number of channels, provide the status of
the current channel, enable multichannel operation, and set the multi-
channel frame delay.
Master Clock Divider Registers (DIVx). The
sor values that determine frequencies for internally-generated clocks and
frame syncs. If your system requires more precision and less noise and jit-
ter, refer to Chapter 14, Precision Clock
Clocking
The fundamental timing clock of the SPORT modules is peripheral
clock/4 ( /4). Each serial port has a clock signal (
PCLK
transmitting and receiving data on the two associated data signals. The
clock signals are configured by the
trol registers. A single clock signal clocks both A and B data signals (either
configured as inputs or outputs) to receive or transmit data at the same
rate.

Master Clock

The bit field specifies how many times the processor's internal
CLKDIV
clock ( ) is divided to generate the transmit and receive clocks. The
PCLK
10-8
www.BDTIC.com/ADI
Table 10-7 on page 10-24
10-21.
) are used to observe and control error handling during
"Error Status" on page
ICLK
ADSP-214xx SHARC Processor Hardware Reference
and "Operation
"Error Detection"
10-53.
registers contain divi-
DIVx
Generator.
SPORTx_CLK
and bits of the
CKRE
SPER-
) for
con-
SPCTLx