Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 797

SPI_FLG0_O
0 1
SPI_CLK_O
SPI_MOSI_O
SPI_MISO_i
Figure 23-4. SPI Master Mode Booting Using Various Serial Devices
Slave Boot Mode
In slave boot mode, the host processor initiates the booting operation by
activating the
SPICLK
low state. The 256-word kernel is loaded 32 bits at a time, through the
SPI receive shift register (
words) properly, the SPI DMA initially loads a DMA count of 0x180
(384) 32-bit words, which is equivalent to 0x100 (256) 48-bit words.
Note that for SPI slave boot
has deasserted.

When in SPI slave booting mode, the
trolled by the SPI host to initiate the boot transfers as shown in
Table 23-9.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
4 5 6 7
8-BIT INSTRUCTION
signal and asserting the
). To receive 256 instructions (48-bit
RXSR
SPIDS
8 9 22 23 24
16-BIT ADDRESS
signal to the active
SPIDS
should only be asserted after
SPI_DS_I
System Design
25 26 27 28 29 30
VALID EPROM BITS
RESETOUT
input signal is con-
23-15
31
WORD