Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 608

Operating Modes
In the bypass mode, if the
a one-shot pulse is generated. This one-shot pulse has the duration equal
to the period of
either at the falling or rising edge of the input clock, depending on the
value of the
INVFSx
equal to the period of the SRU source signal
the second rising edge of
input. When the
edge of
MISCAx_I
input.

Notice a strobe period is defined to be the period of the FS input
clock signal specified by the
C LOCK INPUT
FOR FRAME SYNC
MISCA2_I
FRAME SYNC OUTPUT
(INVFSA = 0, STROBEA = 1)
FRAME SYNC OUTPUT
(INVFSA = 1, STROBEA = 1)
Figure 14-4. One Shot Mode PCG A (MISCA2_I input)
External Event Trigger
The trigger with the external clock is enabled by setting bits 0 and 16 of
the register.
PCG_SYNC
14-14
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STROBEx
for the PCGx unit. This pulse is generated
MISCAx_I
bit of the
PCG_PW
MISCAx_I
bit is set, the pulse begins at the second rising
INVFSx
coinciding with or following a falling edge of the clock
WHEN MISCA2 INPUT IS LOW,
OUTPUTS ARE ALSO LOW
ADSP-214xx SHARC Processor Hardware Reference
bit of register is set to 1, then
PCG_PWx
register. The output pulse width is
. The pulse begins at
MISCAx_I
following a rising edge of the clock
bit (
FSxSOURCE PCG_CTLx1
registers).