Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 683

Pin Descriptions
The pin descriptions for the shift register are described in the
ADSP-2147x data sheet.
SRU Programming
To use the shift register, route the required inputs using the SRU as
described in Table
• The
SR_SCLK
source except in the case where
SR_SCLK
/ then SPORT0–7 generates the
PCGA B
SR_SCLK
the
SR_SDI
• Configure
SR_LAT_I
• The
SR_CTL
domain. There may be timing violations for signals crossing
PCLK
domain to the
PCLK
this first program
isters and then drive on
Table 17-2. SR DAI/SRU Connections
Internal Nodes
Inputs
SR_SCLK_I
SR_LAT_I
SR_DAT_I
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
17-2, taking not of the following.
, , and
SR_LAT SR_SDI
and come from
SR_LAT
and come from
SR_LAT
signal.
= 1 when using SPORT as a source of
CKRE
, and signals.
SR_DAT_I
,
SRU_CLK_SHREG
SR_SDCLK_I
,
SR_CTL SRU_CLK_SHREG
SR_SDCLK_I
DAI Group
G
Shift Register – ADSP-2147x
inputs must come from the same
comes from
SR_SCLK
/ . If
PCGA B SR_SCLK
and
SR_LAT
/ , then SPORT0–7 generates
PCGA B
, and
SRU_DAT_SHREG
and domain. To avoid
SR_LAT_I
, and
, , and
SR_LAT_I
SRU Register
SRU_CLK_SHREG
SRU_DAT_SHREG
/ or
PCGA B
comes from
signals. If
SR_SDI
,
SR_SCLK_I
registers are in
reg-
SRU_DAT_SHREG
.
SR_SDI_I
17-3