Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 832

System and Power Management Registers
Table A-2. SYSCTL Register Bit Descriptions (Cont'd)
Bit Name
23–21 EPDATA
24 PWM0EN
25 PWM1EN
26 PWM2EN
27 PWM3EN
29–28 Reserved
30 PWMOND-
PIEN
31 Reserved
ADSP-2146x Power Management Registers
The registers described in the following sections are specific to the
ADSP-2146x processors.
A-6
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Description
AMI Mode Select.
Selects between multiplexed AMI, Flags, PWM and PDAP interfaces
on the AMI bus.
For detailed programming modes for these bits, see
External Port Pins" on page
Pulse Width Modulation Select.
When set (=1), enables PWM3–0.
Multiplexing" on page 23-28.
ADSP-2148x.
Pulse Width Modulation Select.
When set (=1), enables PWM7–4.
Multiplexing" on page 23-28.
Pulse Width Modulation Select.
When set (=1), enables PWM11–8.
Multiplexing" on page 23-28.
Pulse Width Modulation Select.
When set (=1), enables PWM15–12.
Multiplexing" on page 23-28.
Enable PWM Signals on the DPI Pins. Enables the PWM signals on
DPI pins. When this bit is set (=1), the flags (4–15) which are routed
to the DPI pins can be used as PWM signals. Applicable only for
ADSP-2148x and ADSP-2147x processors.
ADSP-214xx SHARC Processor Hardware Reference
"Multiplexed
23-30.
For more information, see "Pin
Reserved for ADSP-2147x and
For more information, see "Pin
For more information, see "Pin
For more information, see "Pin