Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 980

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Peripherals Routed Through the DAI

Table A-84. SPCTLx Register Bit Descriptions (Standard Serial Mode)

(RW) (Cont'd)

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16-Bit to 32-Bit Word Packing Enable. When PACK = 1, two succes-

sive received words are packed into a single 32-bit word, and each

32-bit word is unpacked and transmitted as two 16-bit words.

The first 16-bit (or smaller) word is right-justified in bits 15–0 of the

packed word, and the second 16-bit (or smaller) word is right-justified

in bits 31–16. This applies to both receive (packing) and transmit

(unpacking) operations. Companding can be used with word packing or

unpacking. When SPORT data packing is enabled, the transmit and

receive interrupts are generated for the 32-bit packed words, not for

each 16-bit word. Note that when 16-bit received data is packed into

32-bit words and stored in NW-word space in internal memory, the

16-bit words can be read or written with SW-space addresses.

0 = Disable 16- to 32-bit word packing

1 = Enable 16- to 32-bit word packing

Internal Clock Select. When ICLK is set (=1), the clock signal is gener-

ated internally by the processor and the SPORTx_CLK_O signals are

outputs. The clock frequency is determined by the value of the serial

clock divisor (CLKDIV) in the DIVx registers. When ICLK is cleared

(=0), the clock signal is accepted as an input on the SPORTx_CLK_I

signals, and the serial clock divisors in the DIVx registers are ignored.

Note the externally-generated serial clock does not need to be synchro-

nous with the processor's system clock.

0 = Select external transmit clock

1 = Select internal transmit clock

Sport Operation Mode.

0 = DSP serial/multichannel mode if cleared

ADSP-214xx SHARC Processor Hardware Reference

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