Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 377

Pulse Width Modulation
PWMPERIOD PWMPERIOD PWMPERIOD
+ +
2 0 2 0 2
count
PWMCHA
PWMCHA
PWM_AH
PWM_AL
2xPWMDT 2xPWMDT
PWMPHASE
PWMPERIOD
PWMPERIOD
PWM INTERRUPT
LATCH BIT
Figure 7-2. Center-Aligned Paired PWM in Single Update Mode,
Low Polarity
The resulting on-times (active low) of the PWM signals over the full
PWM period (two half periods) produced by the PWM timing unit and
illustrated in Figure 7-2 may be written as:
The range of T is:
AH
[ × × ]
0 2 – PWMPERIOD t
PCLK
and the corresponding duty cycles are:
( × ( ) ×
T PWMPERIOD PWMCHA PWMDT t
2
= – +
AH PCLK
ADSP-214xx SHARC Processor Hardware Reference 7-9
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