Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 186

DDR2 DRAM Controller (ADSP-2146x)
The subsequent burst bit data are issued on successive edges of
until the burst length is completed. When the burst has finished, any
additional data supplied to the
signal is ignored after the burst write operation is complete. The time
from the completion of the burst write to bank precharge is the write
recovery time (WR).
T0
DDR2_CLKx/
DDR2_CLKx
ACTIVE
CMD
N
DDR2_DQS/
DDR2_DQS
DQS
CAS Latency (CL) = 3
Additive Latence (AL) = 2
WRITE latency = AL + CL - 1 = 4
Figure 3-13. Burst Write
Auto-Refresh
The DDR2 internally increments the refresh address counter and causes a
CAS before RAS (CBR) refresh to occur internally for that address when
the auto-refresh command is given. The controller generates an
auto-refresh command after the refresh counter times out. The
in the
DDR2RRC
within the t
REF
Before executing the auto-refresh command, the DDR controller executes
a pre-charge all command to all external banks. The next activate com-
mand is not given until the t
commands are also issued by the controller as part of the power-up
sequence and after exiting self-refresh mode.
3-56
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DDR2_DATA
T1 T2
WRITE
NOP
N
t
RCD (min)
AL = 2
WL = AL + CL - 1 = 4
register must be set so that all addresses are refreshed
period specified in the DDR2 timing specifications.
specification is met. Auto-refresh
RFC
ADSP-214xx SHARC Processor Hardware Reference
pins is ignored. The
T3 T4
NOP NOP NOP
CL - 1 = 2
D in
DDR2_DQS
DDR2_DATA
T5 T6
NOP NOP
D in D in
D in
n n+1 n+2 n+3
value
RDIV
T7