Asynchronous Reads; Asynchronous Writes - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Asynchronous Memory Interface
The external interface follows standard asynchronous SRAM access proto-
col. The programmable wait states, hold cycle and idle cycles are provided
to interface memories of different access times. To extend access the
signal can be pulled low by the external device as an alternative to using
wait states.

Asynchronous Reads

Figure 3-3 shows an asynchronous read bus cycle. Asynchronous read bus
cycles proceed as follows.
1. At the start of the setup period,
bus becomes valid.
2. At the beginning of the read access period and after the 3rd cycles,
deasserts.
AMI_RD
3. At the beginning of the hold period, read data is sampled on the
rising edge of the
4. At the end of the hold period, some
case the read is followed by a write. Also,
next cycle is to the same memory bank.

Asynchronous Writes

Figure 3-4 shows an asynchronous write bus cycle. Asynchronous write
bus cycles proceed as follows.
1. At the start of the setup period,
become valid.
2. At the beginning of the write access period,
3. At the beginning of the hold period,
4. One hold cycle is introduced before next access can happen. Also,
deasserts unless the next cycle is to the same memory bank.
MSx
3-12
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MSx
clock.
SDCLK
MSx
ADSP-214xx SHARC Processor Hardware Reference
and assert. The address
AMI_RD
cycles happened in the
IDLE
deasserts unless the
MSx
, the address bus, data buses,
asserts.
WR
deasserts.
WR
ACK