Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 317

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Effect Latency

The total effect latency is a combination of the write effect latency (core

access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming

FFT Accelerator Effect Latency

After the FFT registers are configured the effect latency is 1.5

minimum and 2

an effect latency of two

selecting an accelerator before accessing any of its registers.

Programming Model

There are two separate programming models, one for a FFT that fits in the

accelerator's internal memory (N = 256 points or less) and one for a FFT

that is larger than the accelerator's internal memory (N = 512 points or

more). In both models, is assumed that the accelerator starts in idle mode.

N <= 256, No Repeat

For details on the storage format of the coefficients see

Storage" on page

1. Configure the

accelerator.

2. Program the

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

cycles maximum. Writes to the

cycles. Wait for at least four

FFT/FIR/IIR Hardware Modules

"Internal Memory

cycles after

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