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24-bit word widths. The over sampling clock is also selected by the trans-
mitter control register.
BIT REGISTERS
LRCLK
24
LEFT DATA
24
RIGHT DATA
3
U, V, CS LEFT
3
U, V, CS RIGHT
EXT SYNC
BIPHASE_TX_CLK
FREQMULT 2
Figure 13-2. AES3 Output Block
Input Data Format
The
Figure 13-3
to the S/PDIF transmitter using a variety of interfaces.
Bits 31–8: 24-Bit Audio Data
Figure 13-3. Data Packing for I
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
STATUS/USER
BLK_START
INTERNAL
BUFFER
TX_ENABLE
SAMPLE BIT
SAMPLE
LR
U, V, CS BITS
BIPHASE_CLK
TX_CLK_GEN_SYNC
through
Figure 13-7
Validity Bit
2
S and Left-Justified Format
Sony/Philips Digital Interface
BLK_START_O
BIPHASE
BIPHASE_OUT
ENCODER
7
M_COUNT
shows the format of data that is sent
7
6
5
4
BITS 3–0
User Data
Channel Status
Block Start
Padding (zero)
DAI
13-9
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