Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 529

PDAP Port Selection
The input to channel 0 of the IDP is multiplexed, and may be used either
in the serial mode or in a direct parallel input mode. Setting the
bit high disables the connection of SIP0 to channel 0 of the FIFO. The
data inputs can come either from the DAI pins or the external port
pins. This is selected by the
Figure 11-2 illustrates the data flow for IDP channel 0, where either the
PDAP or serial input can be selected.
DATA10
IDP0_CLK_I
DATA11
IDP0_FS_I
DATA31-12
DAI_PB20-1
Figure 11-2. PDAP Port (Detail of IDP Channel 0)
Data Hold
When the
PDAP_HOLD
and no new data is read from the input pins. The packing unit operates as
normal, but it pauses and waits for the
and waits for the correct number of distinct input samples before passing
the packed data to the FIFO.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
PDAP_PP_SELECT
PDAP_CLK_I
PDAP Control
PDAP_HOLD_I
INPUT DATA
LATCH
CHANNEL 0
signal is high, all latching clock edges are ignored
bit in the
PDAP_CTL
DAI
UNIT
PDAP_STRB_O
32-BIT
DATA
DATA
MASK
PACKING
UNIT
UNIT
signal to be deasserted
PDAP_HOLD
Input Data Port
PDAP_EN
ADDR
register.
DATA8
IDP_FIFO
SIP
DATA
11-9