Effective Accuracy - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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configuration registers, duty cycle registers and the
result, it is possible to alter both the characteristics (switching frequency
and dead time) as well as the output duty cycles at the mid-point of each
PWM cycle. Consequently, it is possible to produce PWM switching pat-
terns that are no longer symmetrical about the mid-point of the period
(asymmetrical PWM patterns).
In double update mode, it may be necessary to know whether operation at
any point in time is in either the first half or the second half of the PWM
cycle. This information is provided by the
register which is cleared during operation in the first half of each PWM
period (between the rising edge of the original PWM interrupt latch pulse
and the rising edge of the new PWM interrupt pulse introduced in double
update mode). The
operation in the second half of each PWM period. This status bit allows
programs to make a determination of the particular half-cycle during
implementation of the PWM interrupt service routine, if required.
The advantage of the double update mode is that the PWM process can
produce lower harmonic voltages and faster control bandwidths are possi-
ble. However, for a given PWM switching frequency, the interrupts occur
at twice the rate as in double update mode. Since new duty cycle values
must be computed in each PWM interrupt service routine, there is a larger
computational burden on the processor in the double update mode.
Alternatively, the same PWM update rate may be maintained at half the
switching frequency to give lower switching losses.

Effective Accuracy

The PWM has 16-bit resolution but accuracy is dependent on the PWM
period. In single update mode, the same values of
to define the on times in both half cycles of the PWM period. As a result,
the effective accuracy of the PWM generation process is 2 x
for a 200 MHz clock). Incrementing one of the duty cycle registers by one
changes the resultant on time of the associated PWM signals by 2 x
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
bit of the the
PWMPHASE
Pulse Width Modulation
register. As a
PWMSEG
bit of the
PWMPHASE
register is set during
PWMSTAT
and
PWMA
PWMB
PCLK
PWMSTAT
are used
(or 10 ns
PCLK
7-23

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