Output Clock Generator Programming Model; Self-Refresh Mode - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Output Clock Generator Programming Model

The following non VCO programming sequence may be used to change
the output generator clock and the core-to-peripheral clock ratio (for
example the SDRAM clock). Note that if your program is only changing
the PLL output divider, programs do not need to wait 4096
(required only if the PLL multiplier or the
1. Disable the peripheral (SDRAM). Note that the peripherals cannot
be enabled when changing clock ratio.
2. Select the PLL divider by setting the
register).
PMCTL
3. Select the clock divider (
bits (
PMCTL
4. Wait 15
any valid instructions.
5. Enable the peripheral (SDRAM).
The new divisor ratios are picked up on the fly and the clocks
smoothly transition to their new values after a maximum of 15 core
clock
CCLK

Self-Refresh Mode

The following steps are required when enter and releasing self-refresh
mode.
1. Set the
SDSRF
2. Poll the
mine if the SDRAM has already entered self-refresh mode.
3. Set the
DSDCTL
ADSP-214xx SHARC Processor Hardware Reference
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CCLK
register).
cycles. During this time, programs must not execute
CCLK
cycles.
bit to enter self-refresh mode.
bit in the SDRAM status register (
SDSRA
bit to freeze
bit is modified).
INDIV
bits (bits 6–7 in the
PLLDx
to SDRAM ratio) by setting the ratio
(optional).
SDCLK
External Port
cycles
CLKIN
) to deter-
SDSTAT
3-127