Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 700

Interrupts
Emulation Considerations
An emulation halt can optionally mask all RTC interrupts by setting the
bit in
EMU_INTDIS
Effect Latency
The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).
Write Effect Latency
For details on write effect latency, see the SHARC Processor Programming
Reference.
Real-Time Clock Effect Latency
After the RTC registers are configured the effect latency is 2
Programming Model
Writes of the alarm, clock, stopwatch and initialization registers is per-
formed in a two step sequence:
1. The desired values are programmed into a shadow register in the
processor's core power domain and operating on the its peripheral
clock (
PCLK
2. The contents of the shadow register are synchronized onto the con-
tents of the RTC's internal clock register which operates on the 1
Hz clock in the RTC power domain.
18-12
www.BDTIC.com/ADI
register.
RTC_CTL
).
ADSP-214xx SHARC Processor Hardware Reference
cycles.
PCLK