Functional Description; Data Transfer Types; Data Buffer - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Functional Description

The MTM module owns two DMA channels one for read and one for
write including a data buffer which stores up to 2x32-bit data. After the
DMA is configured, the read DMA channel fills the buffer with 64-bit
data. After this transfer, the write DMA channel becomes active and emp-
ties the buffer according to its destination. This procedure is repeated
until the DMA count is zero.
The memory-to-memory DMA controller is capable of transferring 64-bit
bursts of data between internal memories.

The MTM controller supports data in normal word address space
only (32-bit). External to external DMA transfers are not
supported.

Data Transfer Types

The memory-to-memory DMA controller is capable of transferring 64-bit
bursts of data between internal memories.

Data Buffer

The bit in the
MTMFLUSH
reset the read/write pointers. Setting and resetting the
starts and stops the DMA transfer, so it is always better to flush the FIFO
along with
MTMDEN
Note that the
MTMFLUSH
Otherwise the FIFO is continuously flushed leading to DMA data
corruption.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Memory-to-Memory Port DMA
register can be set to flush the FIFO and
MTMCTL
reset.
bit should not be set along with the
bit only
MTMDEN
bit set.
MTMDEN
5-3