Standard Serial Mode; Timing Control Bits - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table 10-8. Channel Order First
OPMODE
Left-Justified
Packed
2
I S

Standard Serial Mode

The standard serial mode lets programs configure serial ports for use by a
variety of serial devices such as serial data converters and audio codecs. In
order to connect to these devices, a variety of clocking, framing, and data
formatting options are available.

Timing Control Bits

Several bits in the
mode operation:
• Internal Clock (
• Internal Frame Sync (
• Frame Sync Required (
• Sampling Edges Frame Sync/data (
• Logic Level Frame Sync (
• Late Frame Sync (
• Word length (
• Word Order (
• Word Packing (
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
L_FIRST = 0
Data first after rising edge
Data first after rising edge
Data first after falling edge
register enable and configure standard serial
SPCTLx
)
ICLK
)
IFS
)
FSR
)
LFS
)
LAFS
, 3–32 bits)
SLEN
)
LSBF
)
PACK
L_FIRST = 1
Data first after falling edge
Data first after falling edge
Data first after rising edge
)
CKRE
Serial Ports
10-25