Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 839

31 30
SDCKR
Core Clock to SDRAM Clock
15
PLLBP
PLL Bypass
DIVEN
PLL Divider Enable
INDIV
Input Divider
Figure A-4. PMCTL Register
Table A-5. PMCTL Register Bit Descriptions (RW)
Bit Name
5–0 PLLM
7–6 PLLD
8 INDIV
ADSP-214xx SHARC Processor Hardware Reference
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29 28 27 26 25 24 23 22
14 13 12 11 10 9 8 7
Description
PLL Multiplier.
PLLM = 0 PLL multiplier = 128
0<PLLM<63 PLL multiplier = 2
Reset value = CLK_CFG1–0
00 = 001000 = 8x
01 = 100000 = 32x
10 = 010000 = 16x
11 = 001000 = 8x
PLL Divider (Output Clock Post Divider).
00 = clock divider = 2
01 = clock divider = 4
10 = clock divider = 8
11 = clock divider = 16
PLL Input Clock Pre Divider.
0 = Divide by 1
1 = Divide by 2
Registers Reference
21 20 19 18 17 16
CRAT (17–16)
PLL Clock Ratio
6 5 4 3 2 1 0
PLLM (5–0)
PLL Multiplier
PLLD (7–6)
PLL Divider
×
PLLM
A-13