Mtm Throughput; Effect Latency; Write Effect Latency; Mtm Effect Latency - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

MTM Throughput

Data throughput for internal to internal transfers is 12
64-bit data.

Effect Latency

The total effect latency is a combination of the write effect latency (core
access) plus the peripheral effect latency (peripheral specific).

Write Effect Latency

For details on write effect latency, see the SHARC Processor Programming
Reference.

MTM Effect Latency

After the MTM register is configured the effect latency is 1.5
minimum and 2

Programming Model

This data transfer can be set up using the following procedure.
1. Program the DMA registers for both channels.
2. Set (=1) the
FIFO and reset the read/write pointers.
3. Set (=1) the
A two-deep, 32-bit FIFO regulates the data transfer through the
DMA channels.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
cycles maximum.
PCLK
bit (bit 1) in the
MTMFLUSH
bit in the
MTMEN
Memory-to-Memory Port DMA
register to flush the
MTMCTL
register.
MTMCTL
cycles for
PCLK
cycles
PCLK
5-5