Data Transfer; Link Buffers - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Table of Contents

The following is a list of the areas of concern when a program implements

a software protocol scheme for token passing:

• The program must make sure that both link ports are not enabled

to transmit at the same time. In the event that this occurs, data

may be transmitted and lost due to the fact that neither link port is

ensure that the master becomes the slave before the slave becomes

the master, avoiding the two transmitter conflict.

• The program must make sure that the link interrupt selection

matches the application. If a status detection scheme using the sta-

tus bits is to be used, it is important to note the following: If a link

port that is configured to receive is disabled while

there is an RC delay before the external pulldown resistor on

(if enabled) can pull the value below logic threshold. If the

status bit is unmasked (in this instance), then an LSR is latched

• The program must make sure that synchronization is not disrupted

by unrelated influences at critical sections where timing control

loops are used to synchronize parallel code execution. Disabling of

nested interrupts is one technique to control this.

Data Transfer

The link ports are able to transfer data using DMA and core.

The transmit buffer registers (

buffer the data flow through the link port. The transmit and receive

ADSP-214xx SHARC Processor Hardware Reference

www.BDTIC.com/ADI

. In the example, the

interrupt may be serviced, even though unintended, if

) and receive buffer registers (

Link Ports—ADSP-2146x

status bit is polled to

is asserted,

Table of Contents