Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 575

clock, frame sync, data, and
required) inputs also need to be routed through SRU (see
Table 13-4. S/PDIF DAI/SRU Transmitter Signal Connections
Internal Node
Inputs
DIT_CLK_I
DIT_HFCLK_I
DIT_EXTSYNC_I
DIT_DAT_I
DIT_FS_I
Outputs
DIT_O
DIT_BLKSTART_O
The SRU (signal routing unit) needs to be programmed in order to con-
nect the S/PDIF receiver to the output pins or any other peripherals and
also for the connection to the input biphase stream.
Program the corresponding SRU registers to connect the outputs to the
required destinations
external PLL clock inputs to the receiver are routed through the signal
routing unit (SRU). The extracted clock, frame sync, and data are also
routed through the SRU.
Table 13-5. S/PDIF DAI/SRU Receiver Signal Connections
Internal Node
Inputs
SPDIF_EXTPLLCLK_I
DIR_I
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Sony/Philips Digital Interface
(if external synchronization is
EXT_SYNC
DAI Group
Group A
Group B
Group C
Group B, D
Group D, E
(Table 13-5). The biphase encoded data and the
DAI Group
Group A
Group C
Table 13-4).
SRU Register
SRU_CLK4–2
SRU_DAT4
SRU_FS2
SRU Register
SRU_CLK4
SRU_DAT5
13-5