Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 215

Whenever the
AMITX
access from the processor core can write new data into the AMI. If the reg-
ister is full, further writes from the core (or DMA controller) are stalled.

For core and DMA access, the received data is also unpacked,
depending on the setting of the
is dependent on the
DMA Buffer
The external port supports two DMA channels, each populated with a
data buffer (
DFEP1–0
can be read in the
AMI, SDRAM or DDR2 transfers.
Port DMA" on page 3-100.
Core Access
For core-driven external port transfers, the instruction needs to read or
write from a valid external port address.
External Port Dual Data Fetch
The dual data fetch instruction (Type 1) allows the processor to access
external data from both DAGs. In such an instruction, the accesses are
executed sequentially (not simultaneously as in internal memory). For
example:
r4=r2+r3, r2=dm(i6,m6), r3=pm(i10,m10);
The DAG1 access (operand
DAG2 access (operand
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
buffer is empty, the DMA controller or a direct
bit in
MSWF
). Each data buffer is 6 locations deep and its status
register. Note the DMA channels are valid for
DMACx
For more information, see "External
) is executed first followed by the second
r2
).
r3
bit. The order of unpacking
PKDIS
registers.
AMICTLx
External Port
3-85