Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 394

Interrupts
interrupts and is unmasked in the core. The
are also written, depending on the system configuration and modes. Dur-
ing the PWM interrupt driven control loop, only the
are typically updated. The
system implementations requiring output crossover.
For interrupt execution, the specific
register must be set including the
PWMCTLx
on the programmable interrupt to be used.
Whenever a period starts, the PWM interrupt is generated. The interrupt
latch bit is set 1
PWM units share the same interrupt vector, the interrupt service routine
should read the
interrupt. Next, the ISR needs to clear the status bits of the
ister by explicitly writing 1 into the status bit (W1C) as shown in
Listing 7-1.
Listing 7-1. Writing 1 Into the Status Bit
GPWM_ISR:
ustat2=dm(PWMGSTAT);
bit tst ustat2 PWM_STAT2;
if tf jump PWM2_ISR;
instruction;
instruction;
PWM2_ISR:
r1=PWM_STAT2;
dm(PWMGSTAT)=r1; /* W1C to clear PWM2 interrupt */
r10=dm(PWMCTL2); /* dummy read for write latency */
instruction;
rti;
7-26
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register may also be updated for other
PWMSEG
cycle after the PWM counter resumes. Since all four
PCLK
register in order to determine the source of the
PWMGSTAT
/* read global status reg */
/* test PWM2 status */
/* jump to PWM2 routine */
ADSP-214xx SHARC Processor Hardware Reference
and
PWMSEG
PWMCHx
bit in the corresponding
PWM_IRQEN
or
IMASK LIRPTL
registers
PWMCHx
duty values
registers based
reg-
PWMGSTAT