Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 818

Table of Contents

High Frequency Design

Asynchronous Inputs

The processor has several asynchronous inputs such as

and the DAI/DPI pins and reset inputs

which can be asserted in arbitrary phase to the reference clocks. The pro-

cessor synchronizes the reset inputs to the

peripheral inputs are synchronized to the

The delay associated with recognition is called the synchronization delay.

Any asynchronous input must be valid prior to the recognition point in a

particular cycle. If an input does not meet the setup time on a given cycle,

it may be recognized in the current cycle or during the next cycle.

To ensure recognition of an asynchronous input, it must be asserted for at

cycle plus setup and hold time, except for

must be asserted for at least four

time prior to recognition (the setup and hold time) is specified in the

appropriate product data sheet.

Decoupling and Grounding

Designs should use an absolute minimum of four bulk capacitors

(2 × 10 µF for

mum of 20 × 10nF ceramic bypass capacitors (5 per chip corner for

Capacitors type, value and placement is critical—especially for floating

point computations, which draw more power. If the bulk/bypass capaci-

tors are insufficient, the power rails may drop, causing errors. Therefore

sufficient capacitor backup is important.

www.BDTIC.com/ADI

and 2 × 10 µF for V

ADSP-214xx SHARC Processor Hardware Reference

, running reset

input while the

prior to recognizing them.

processor cycles. The minimum

). Furthermore a mini-

Chapters

Table of Contents