Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 774

Power Management

The advantage of the delayed core reset is that the PLL can be reset
any number of times without having to power down the system. If
there is a brownout situation, the external watchdog circuit only
has to control the
power-up, see the appropriate product data sheet.
Power Management
The processor allows systems to shut down the clock to the different mod-
ules in the peripheral domain in order to save power if the peripherals are
not required by the application.
Peripherals
All internal clocks to the peripherals are enabled by default. However,
they can be disabled using the
The register allow programs to disable the clock source to a partic-
PMCTL1
ular processor peripheral (for example the external port) to further
conserve power. Programs can use the
peripheral off after the application no longer needs it. For a complete reg-
ister description, see
page A-6 and "ADSP-2147x/ADSP-2148x Power Management Registers"
on page A-12.
DAI Routing Unit
To further preserve power, the clock to the DAI routing unit can be dis-
abled using the
requires the SPORTs, the DAI system routing can be configured and then
bit 4 can be cleared to disable the routing block. Note that the SPORT
continues to operate as long as the SPORT clocks themselves are not shut
down.
22-10
www.BDTIC.com/ADI
signal. For more information on device
RESET
PMCTL1
"ADSP-2146x Power Management Registers" on
bit in the
DAIOFF PMCTL1
ADSP-214xx SHARC Processor Hardware Reference
register.
register to turn the specific
PMCTL1
register. If, for example, a system