Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 609

Since the rising edge of the external clock is used to synchronize with the
frame sync, the frame sync output is not generated until a rising edge of
the external clock is sensed
TRIGGER DELAY
CLKIN
(INPUT)
EXT. TRIGGER
(INPUT)
FSA
(OUTPUT)
Figure 14-5. FS Output Synchronization With External Trigger Input
External Event Trigger Delay
The time delay between the rising trigger edge and the start of
varies between 2.5 to 3.5 input clock periods. If the input clock and the
trigger signal are synchronous, the delay is 3 input clock periods. The fol-
lowing cases need to be considered:
• is the input source. In this case if the given trigger event is
PCLK
synchronous to
nal is asynchronous with
periods to 3.5
edge occurs in the positive half cycle or negative half cycle of
• is the input source. In this case if the given trigger signal is
CLKIN
synchronous to
asynchronous to
ods to 3.5
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
(Figure 14-5).
, the delay is 3
PCLK
PCLK
periods. (It depends on whether the trigger
PCLK
, the delay is 3
CLKIN
, the delay can vary between 2.5
CLKIN
periods.
CLKIN
Precision Clock Generator
periods. If the trigger sig-
PCLK
, the delay varies from 2.5
periods. But if they are
CLKIN
/
SCLK FS
PCLK
.)
PCLK
peri-
CLKIN
14-15