Refresh Rate Control - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

SDRAM Controller (ADSP-2147x/ADSP-2148x)
Table 3-10 where
and = 11 (11 bits).
SDCAW1–0
Table 3-10. Page Interleaving Map (2K Page Size)
Pin
A[18]
A[17]
A[13]
A[12]
A[11]
SDA10
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]

Refresh Rate Control

The SDRAM refresh rate control register provides a flexible mechanism
for specifying auto-refresh timing. The SDC provides a programmable
refresh counter which has a period based on the value programmed into
the lower 12 bits of this register. This coordinates the supplied clock rate
with the SDRAM device's required refresh rate.
3-32
www.BDTIC.com/ADI
= 0,
SDADDRMODE
Column Address Row Address
IA[20]
IA[19]
IA[8] IA[18]
IA[7] IA[17]
IA[6] IA[16]
IA[5] IA[15]
IA[4] IA[14]
IA[3] IA[13]
IA[2] IA[12]
IA[1] IA[11]
IA[0] IA[10]
1/0 IA[9]
ADSP-214xx SHARC Processor Hardware Reference
= 1,
X16DE SDRAW2–0
Bank Address
IA[22]
IA[21]
= 100 (12 bits),
Pins of SDRAM
BA[1]
BA[0]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]