Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 353

IIR CONTROL
REGISTERS
BIQUAD
BIQUAD
BIQUAD
C
STAGE 1
O
BIQUAD
E
STAGE 2
F
BIQUAD
F
STAGE 3
I
C
.
I
.
E
.
N
T
S
BIQUAD
STAGE N
Figure 6-9. IIR Accelerator Block Diagram
The IIR accelerator is implemented using Transposed Direct Form II
biquad which has less coefficient sensitivity.
flow graph for the biquad structure.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
CORE PMD/DMD
BUS
IIR CONTROLLER
RESULT
REGISTER
BIQUAD
COEFF
COMPUTE
ACCESS
UNIT
CONTROL
(1 MAC)
FFT/FIR/IIR Hardware Modules
IOD0
BUS
DMA
CONTROLLER
DATA
AND
STATE
ACCESS
CONTROL
Figure 6-10
BIQUAD
I
BIQUAD
N
BIQUAD
P
STAGE 1
U
T
BIQUAD
STAGE 2
D
BIQUAD
A
STAGE 3
T
.
A
.
.
&
S
T
A
T
E
BIQUAD
STAGE N
shows the signal
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