Mixing Instructions And Data In External Bank 0; Addressing For Various Memory Sizes - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Mixing Instructions and Data in External Bank 0

It is possible to store both 48-bit instructions as well as 16-bit data in
external memory bank 0. However, care must be taken while specifying
the proper starting addresses if 48-bit instructions are stored or interleaved
with 16-bit data in the same memory bank.
In 16-bit wide external SDRAM/DDR2 memory, one instruction is
packed into three 16-bit memory locations, while 16-bit data occupies
two memory locations.
For example, if 2k instructions are placed in 16-bit wide SDRAM/DDR2
memory starting at the bank 0 (logical address 0x0020 0000 correspond-
ing to physical address 0x0060 0000) and ending at logical address
0x002007FF (corresponding to physical address 0x0060 17FF), then data
buffers can be placed starting at an address that is offset by 3k 16-bit
words (for example, starting at 0x0060 1800).

Addressing for Various Memory Sizes

Table 3-21 provides addressing for various sizes of DDR2 DRAM
memory.
Table 3-21. Translation of Logical to Physical Addressing for DDR2
DDR2 Device Physical Address Range Mapped to
Memory Device
256 Mb (x16) 0x60 0000 – 0x15F FFFF
512 Mb (x16) 0x60 0000 – 0x25F FFFF
1 Gb (x16) 0x60 0000 – 0x45F FFFF
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
External Port
Mapping Between External Port
Address Range and Memory Device
0x20 0000 – 0xFF FFFF
0x00 0000 – 0x1F FFFF
0x020 0000 – 0x1FF FFFF
0x000 0000 – 0x01F FFFF
0x020 0000 – 0x3FF FFFF
0x000 0000 – 0x01F FFFF
3-93