Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 582

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S/PDIF Transmitter

To allow user bit updates, write a 0x1 to the

used for further processing. If the

• At every 192nd Frame end, if

bits are taken from user bits buffers and transmitted. Simultane-

• At every 192nd Frame end, if

bits are updated as zeros and transmitted. The

remains low.

For the first block of transfer, write a one (1) to the

ister and then enable the S/PDIF transmitter.

In general, for the next block, programs can update user bits buffers at any

time during the transfer of the current block (1 block = 192 frames).

There are internal buffers to store the user status bits of the current block

of transfer. In other words, at the beginning of every new block, the user

status bit (

copied to internal buffers and transmitted in each frame during the

Note that since a frame contains 192 bits/8 = 24 bytes, six status/user reg-

isters are required to store each four bytes.

Data Output Mode

Two output data formats are supported by the transmitter; two channel

mode and single-channel double-frequency (SCDF) mode. The output for-

mat is determined by the transmitter control register (

In two channel mode, the left channel (channel A) is transmitted when the

is high and the right channel (channel B) is transmitted when

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ADSP-214xx SHARC Processor Hardware Reference

= 1, then the user status

= 0 then the user status

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