Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 884

ADSP-2147x, ADSP-2148x External Port Registers
Table A-30. SDSTAT1 Register Bit Descriptions (RO) (Cont'd)
Bit Field
23–16
31–24
Refresh Rate Control Register (SDRRC)
The SDRAM refresh rate control register provides a flexible mechanism
for specifying the auto-refresh timing. The SDC provides a programmable
refresh counter which has a period based on the value programmed into
the field of this register, that coordinates the supplied clock rate with
RDIV
the SDRAM device's required refresh rate. This register is shown in
Figure A-26. For information on using the
Optimization" on page
A-58
www.BDTIC.com/ADI
Field Name Description
External Bank 2 External Bank 0 Active/Precharge State.
Status xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
...
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
External Bank 3 External Bank 0 Active/Precharge State.
Status xxx1 = Internal bank 0 in open state
xxx0 = Internal bank 0 in precharge state
xx1x = Internal bank 1 in open state
xx0x = Internal bank 1 in precharge state
...
1xxx = Internal bank 7 in open state
0xxx = Internal bank 7 in precharge state
3-40.
ADSP-214xx SHARC Processor Hardware Reference
bit see "SDRAM Read
SMODIFY