Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 596

Features
Table 14-1. PCG Specifications (Cont'd)
Feature
Access Type
Data Buffer
Core Data Access
DMA Data Access
DMA Channels
DMA Chaining
Boot Capable
Local Memory
Clock Operation
Features
The following list describes the features of the precision clock generators.
• Operates on the DAI and DPI units
• PCG input clock selection from
• Provides 4 different clock dividers for serial clock, frame sync,
phase (20-bit) and pulse width (16-bit)
• Phase shift allows adjustment of the frame sync relative to the serial
clock and can be shifted the full period and wrap around
• Provides pulse width control for arbitrary frame sync signal
generation
14-2
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PCGA–B
No
N/A
N/A
N/A
N/A
N/A
No
f
PCLK
CLKIN
ADSP-214xx SHARC Processor Hardware Reference
PCGC–D
No
N/A
N/A
N/A
N/A
N/A
No
f
PCLK
, or external DAI pins
PCLK