Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 872

ADSP-2147x, ADSP-2148x External Port Registers
Table A-25. EPCTL Register Bit Descriptions (RW)
Bit Name
0 B0SD
1 B1SD
2 B2SD
3 B3SD
5–4 EPBR
7–6 DMAPR
10–8 FRZDMA
11 Reserved
A-46
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Description
Select Bank 0 SDRAM.
0 = Bank 0 non-SDRAM
1 = Bank 0 SDRAM
Select Bank 1 SDRAM.
0 = Bank 1 Non-SDRAM
1 = Bank 1 SDRAM
Select Bank 2 SDRAM.
0 = Bank 2 Non-SDRAM
1 = Bank 2 SDRAM
Note that the
MS2
Select Bank 3 SDRAM.
0 = Bank 3 Non-SDRAM
1 = Bank 3 SDRAM
Note that the
MS3
External Port Bus Priority.
00 = Reserved
01 = DMA has high priority
10 = Core has high priority
11 = Rotating priority (default)
External Port Bus Priority.
00 = Priority order from highest to lowest is SPORT, external
port DMA, core
01 = Priority order from highest to lowest is external port
DMA, SPORT, core
10 = Highest priority is core. SPORT and external port DMA
are in rotating priority
11 = Rotating priority (default)
Arbitration Freezing Length for DMA.
000 = No Freezing
001 = 4 Accesses
010 = 8 Accesses
011 = 16 Accesses
100 = 32 Accesses
101 = Page size (SDRAM only1)
110, 111 = Reserved
ADSP-214xx SHARC Processor Hardware Reference
pin is multiplexed.
pin is multiplexed.