Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 196

DDR2 DRAM Controller (ADSP-2146x)
Table 3-15 shows
(11), = 01(four banks).
DDR2BC
Table 3-15. 16-bit Address Mapping (4 Banks, Bank Interleaving)
SHARC Pin
DDR2_BA1
DDR2_BA0
DDR2_ADDR[13]
DDR2_ADDR[12]
DDR2_ADDR[11]
DDR2_ADDR[10]
DDR2_ADDR[9]
DDR2_ADDR[8]
DDR2_ADDR[7]
DDR2_ADDR[6]
DDR2_ADDR[5]
DDR2_ADDR[4]
DDR2_ADDR[3]
DDR2_ADDR[2]
DDR2_ADDR[1]
DDR2_ADDR[0]
Refresh Rate
The DDR2 refresh rate control register (
mechanism for specifying the auto-refresh timing. The DDR2 controller
provides a programmable refresh counter which has a period based on the
value programmed into the
the supplied clock rate with the DDR2 device's required refresh rate.
3-66
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= 1,
DDR2ADDRMODE
Column Address Row Address
IA[9] IA[21]
IA[20]
IA[8] IA[19]
IA[7] IA[18]
IA[6] IA[17]
IA[5] IA[16]
IA[4] IA[15]
IA[3] IA[14]
IA[2] IA[13]
IA[1] IA[12]
IA[0] IA[11]
1/0 IA[10]
field of this register, which coordinates
RDIV
ADSP-214xx SHARC Processor Hardware Reference
= 100 (12),
DDR2RAW
Bank Address
IA[23]
IA[22]
) provides a flexible
DDR2RRC
= 11
DDR2CAW
DDR2 Pin
BA[1]
BA[0]
A[12]
A[11]
A[10]
A[9]
A[8]
A[7]
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]