Functional Description - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

SDRAM Controller (ADSP-2147x/ADSP-2148x)
• Supports up to 254M words of SDRAM memory
• No-burst mode (BL = 1) with sequential burst type
• Open page policy—any open page is closed only if a new access in
another page of the same bank occurs
• Supports multibank operation within the SDRAM
• Uses a programmable refresh counter to coordinate between vary-
ing clock frequencies and the SDRAM's required refresh rate
• Provides multiple timing options to support additional buffers
between the processor and SDRAM
• Allows independent auto-refresh while the asynchronous memory
interface (AMI) has control of the external port
• Supports self-refresh mode for power savings
• Predictive data accesses for higher read data throughput (read
optimization)
• Supports external instruction fetch in bank 0 for ISA and VISA
operation
• Supports 64-bit SIMD mode by the core
• Supports dual data instruction type 1

Functional Description

The SDRAM control signals (
ous operation modes to the SDRAM.
these commands and the pin state for each one.
The configuration is programmed in the
troller can hold off the processor core or DMA controller with an
3-18
www.BDTIC.com/ADI
,
MSx SDCKE
Table 3-5
ADSP-214xx SHARC Processor Hardware Reference
, , ,
SDRAS SDCAS SDWE
provides a reference to
register. The SDRAM con-
SDCTL
) define vari-