N >= 512, Repeat ............................................................. 6-26
Debug Mode ..................................................................... 6-27
FIR Accelerator ........................................................................... 6-28
Features ................................................................................. 6-28
Register Overview ................................................................. 6-29
Clocking ............................................................................... 6-29
Compute Block ................................................................. 6-31
Operating Modes ................................................................... 6-37
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
Contents
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