Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 139

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EP CORE BUS
SPEP (SPORT) BUS
PERIPHERAL
CORE BUS
EP IOP
REGISTER
IOD1 (EP)
DMA BUS
DMA
32
ARBITER
Figure 3-2. External Port Functional Block Diagram (DDR2)
The external port uses a three stage arbitration process whereby all DMA
requests need to pass through the first stage until one request wins. When
this occurs, the winning DMA channel needs to arbitrate with a SPORT
DMA group (for example group A has four DMA channels SP1A/B,
SP0A/B). The winning DMA channel then has a last arbitration process
with the core where the following occurs.
1. External port DMA channels 0/1 rotating priority or high/low
priorities.
2. Winning DMA channel arbitrating with SPORT DMA groups.
3. Winning DMA channel arbitrating with core access.
In the
register, the
EPCTL
bits of
register can be changed only when the external port is idle
EPCTL
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
64
32
DMA
0
DMA
1
and
EBPR
DMAPR
AMI
AMI
ARBITER
DDR2
DDR2
ARBITER
CONTROLLER
bits define the priorities. All the
External Port
ACK
AMI_MS
AMI_WR
AMI_RD
AMI_ADDR
AMI_DATA
4
2
19
2
2
16
3-9
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2_
DDR2
DDR2_

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