Fir Accelerator Tcb - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

TCB Storage

FIR Accelerator TCB

The FIR accelerator DMA supports circular buffer chained DMA.
Table 2-18 shows the required TCBs for chained DMA. The FIR acceler-
ator does not support circular buffering for the coefficient buffer.
Table 2-18. FIR TCBs
Address
CP[18:0]
CP[18:0] + 0x1
CP[18:0] + 0x2
CP[18:0] + 0x3
CP[18:0] + 0x4
CP[18:0] + 0x5
CP[18:0] + 0x6
CP[18:0] + 0x7
CP[18:0] + 0x8
CP[18:0] + 0x9
CP[18:0] + 0xA
CP[18:0] + 0xB
CP[18:0] + 0xC

The
CCFIR
and is decremented from that value onwards. However, coefficient
loading continues until the number of coefficients, equal to the tap
length, are read. This is true even if the
as in the case of a tap length = 10, and the
initialized to 0. The value in the
ficients are loaded.
2-16
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Register
CPFIR
CCFIR
CMFIR
CIFIR
OBFIR
OCFIR
OMFIR
OIFIR
IBFIR
ICFIR
IMFIR
IIFIR
FIRCTL2
register is loaded with the values in the
ADSP-214xx SHARC Processor Hardware Reference
CCFIR
register reaches zero
CCFIR
field in the TCB is
CCFIR
register is –10 after all coef-
CCFIR
TCB field