Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 834

System and Power Management Registers
Table A-3. PMCTL Register Bit Descriptions (RW)
Bit Name
5–0 PLLM
7–6 PLLD
8 INDIV
9 (WO) DIVEN
11–10 Reserved
12 CLKOUTEN
14–13 Reserved
15 PLLBP
A-8
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Description
PLL Multiplier.
PLLM = 0 PLL multiplier = 128
0<PLLM<63 PLL multiplier = 2
Reset value = CLK_CFG1–0
00 = 000110 = 6x
01 = 100000 = 32x
10 = 010000 = 16x
11 = 000110 = 6x (Reserved)
PLL Divider (Output Post Divider).
00 = clock divider = 2
01 = clock divider = 4
10 = clock divider = 8
11 = clock divider = 16
PLL Input Clock Pre Divider.
0 = Divide by 1
1 = Divide by 2
Output Clock Divider Enable.
Enables the post divider settings.
0 = Do not load PLLD
1 = Load PLLD
When the PLL is programmed using the multipliers and the
post dividers, the DIVEN and PLLBP bits should NOT be
programmed in the same core clock cycle.
Clockout Enable. Mux select for CLKOUT and RESETOUT.
0 = Mux output =
1 = Mux output = CLKOUT
The CLKOUT functionality is not characterized and only
used for test purposes.
PLL Bypass Mode Indication.
0 = PLL is in normal mode
1 = Put PLL in bypass mode
ADSP-214xx SHARC Processor Hardware Reference
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PLLM
RESETOUT