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Analog Devices ADSP-21065L EZ-KIT Lite Manual

Analog Devices ADSP-21065L EZ-KIT Lite Manual

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ADSP-21065L EZ-KIT Lite
Evaluation System Manual
Part Number: 82-000490-01
Revision 2.0
January 2003
www.BDTIC.com/ADI

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Summary of Contents for Analog Devices ADSP-21065L EZ-KIT Lite

  • Page 1 ADSP-21065L EZ-KIT Lite Evaluation System Manual Part Number: 82-000490-01 Revision 2.0 January 2003 www.BDTIC.com/ADI...
  • Page 2 Notice Analog Devices, Inc. reserves the right to make changes to or to discontinue any product or service identified in this publication without notice. Analog Devices assumes no liability for Analog Devices applications assistance, customer product design, customer software performance, or infringement of patents or services described herein. In addition, Analog Devices shall not be held liable for special, collateral, incidental or consequential damages in connection with or arising out of the furnishing, performance, or use of this product.

  • Page 3: Table Of Contents

    TABLE OF CONTENTS LIST OF TABLES............................4 LIST OF FIGURES.............................6 INTRODUCTION ..........................7 ..........8 NFORMATION BOUT NALOG EVICES RODUCTS ..................8 ECHNICAL OR USTOMER UPPORT ......................8 URPOSE OF ANUAL ........................8 NTENDED UDIENCE ....................9 ANUAL ONTENTS ESCRIPTION ..................10 OCUMENTS AND ELATED RODUCTS GETTING STARTED........................11 ...........................11 VERVIEW EZ-KIT L...

  • Page 4: List Of Tables

    4.5.5 Primes.dxe ...........................39 4.5.6 Tt.dxe ...........................39 4.5.7 Blink.dxe ..........................39 WORKING WITH EZ-KIT LITE HARDWARE................40 ...........................40 VERVIEW .......................40 YSTEM RCHITECTURE ...........................41 OARD AYOUT 5.3.1 Boot EPROM ........................41 5.3.2 User Push-Button Switches ....................42 5.3.3 User LED’s..........................42 ..........................42 OWER UPPLIES 5.4.1 Power Connector.........................43 5.4.2 European Power Supply Specifications................43 5.4.3...
  • Page 5 2-1 PC M ....................12 ABLE INIMUM ONFIGURATION 2-2 U EZ-KIT L .................15 ABLE ONFIGURABLE ETTINGS 3-1 F ........................18 ABLE UMMARY 3-2 I ................19 ABLE NTERRUPTS SED BY THE ONITOR ROGRAM 3-3 T 3-3. P ......................20 ABLE ABLE OUTINES 3-4 T 3-4.

  • Page 6: List Of Figures

    LIST OF FIGURES 2-1 C ......................14 IGURE OMPONENT ELECTION 3-1 ADSP-21065L EZ-KIT L ......29 IGURE ONITOR ERNEL ODEC RANSFER CHEME 4-1 T .....................33 IGURE ARGET ELECTION IALOG 4-2 T ........................34 IGURE ARGET ESSAGE 4-3 T ..............34 IGURE ARGET OMMUNICATIONS TATUS ESSAGE 5-1 EZ-KIT L ..................40...

  • Page 7: Introduction

    1 INTRODUCTION Thank you for purchasing the ADSP-21065L EZ-KIT Lite evaluation kit. The evaluation board is designed to be used in conjunction with VisualDSP++  development environment and is based on ® the ADSP-21065L SHARC floating-point digital signal processor (DSP). The kit is shipped with an evaluation board and VisualDSP++ software.

  • Page 8: For More Information About Analog Devices, Inc. Products

    ADSP-21065L. 1.4 Intended Audience This manual is a user’s guide and reference to the ADSP-21065L EZ-KIT Lite evaluation board. DSP programmers who are familiar with Analog Devices SHARC architecture, operation, and programming are the primary audience for this manual.

  • Page 9: Manual Contents Description

    1.5 Manual Contents Description This manual contains the following information: • Chapter 1 — Introduction Provides manual information and Analog Devices contact information. • Chapter 2 — Getting Started Provides software and hardware installation procedures, PC system requirements, and basic board information.

  • Page 10: Documents And Related Products

    1.6 Documents and Related Products For more information on the ADSP-21065L and the components of the EZ-KIT Lite system, see the following documents: • ADSP-21065L SHARC User's Manual & Technical Reference • ADSP-21065L • AC’97 SoundPort® The ADSP-2106x family of processors is supported by a complete set of evaluation tools. Software tools include a C compiler, assembler, runtime libraries and librarian, linker, simulator, and PROM splitter.

  • Page 11: Getting Started

    Unused EZ-KIT Lites should be stored in the protective shipping package. The ADSP-21065L EZ-KIT Lite evaluation board package should contain the following items. If any item is missing, contact the vendor where you purchased your EZ-KIT Lite or Analog Devices.

  • Page 12: Pc Configuration

    ADSP-21065L’s on-chip program memory space. If the full VisualDSP++ software suite is purchased, the user will obtain a new serial number from Analog Devices that will lift the restrictions mentioned above. The basic components that are shipped with VisualDSP++ are: •...

  • Page 13: Installation Procedures

    2.5.1 Installing the EZ-KIT Lite Hardware The ADSP-21065L EZ-KIT Lite board is designed to run outside the PC as a stand alone unit. There is no need to remove the chassis from your computer. Use the following steps to connect the EZ-KIT Lite board: 1.
  • Page 14 Figure 2-1 Component Selection www.BDTIC.com/ADI...

  • Page 15: Installing The Visualdsp++ Ez-Kit Lite License

    2.5.3 Installing the VisualDSP++ EZ-KIT Lite License Before the VisualDSP++ software can be used, the license must be installed. To install the EZ-KIT Lite license, follow these steps: 1. Make sure VisualDSP++ has been installed first. 2. Insert the VisualDSP++ CD into the CD-ROM drive if it is not already in the drive.
  • Page 16 the Debugger Help help file. www.BDTIC.com/ADI...

  • Page 17: Using Ez-Kit Lite Software

    This chapter provides monitor level software information on how the EZ-KIT Lite board operates with the installed software. This chapter also provides information that helps the user run his/her own programs on the ADSP-21065L EZ-KIT Lite board. This information appears in the following sections: •...

  • Page 18: Table 3-1 Flag Summary

    • FLAG connect to the LEDs and supply feedback for program execution. For example the user can write code to trigger a flag (and the corresponding LED) when a routine is complete the LED will light. The LED flags are configured through the IOCTL register and are set/read through the IOSTAT register.

  • Page 19: Table 3-2 Interrupts Used By The Monitor Program

    When writing code, these interrupts (and their corresponding vectors) should not be altered. If these vectors are overwritten, the kernel may not work as shown in Table 3-1. For more information on the registers that control interrupts, and a complete list of inter- rupt vector addresses, see Appendix E and F in the ADSP-21065L SHARC Technical Reference.

  • Page 20: Post Routines

    Each of the SPORTs supports three operation modes: DSP SPORT mode, I S mode (an interface commonly used by audio codecs) and TDM (Time Division Multiplex) multichannel mode. For additional information on the serial ports please refer to Chapter 9 of the ADSP-21065L SHARC User’s Manual. Both of the synchronous serial ports are connected to the EMAFE interface.
  • Page 21 3.2.2.1 Memory Checks The monitor program performs some standard memory checks which are as follows: • EPROM • Internal memory • External SDRAM The EPROM test consists of verifying a number in memory. If the monitor code is corrupted, the monitor may crash before reaching the actual program code. These checks include: •...

  • Page 22: Monitor Program Operation

    On power up, the EZ-KIT Lite board defaults to a baud rate of 115200 baud with 8 data bits, 1 stop bit, and no parity. If you want to change this rate change it after the POST is complete use the Settings -> Baud Rate command from the debugger menu bar.

  • Page 23: Ad1819 Transmissions

    The following restrictions should be followed to ensure correct board operation. • The host loses contact with the monitor while the user program is running if the user program disables the UART interrupt or changes the UART interrupt vector. • The host loses contact with the monitor while the program is running and in an ISR when nesting is turned off.

  • Page 24: Running Your Own Programs

    SHARC tools. • Do not run more than one ADSP-21065L EZ-KIT Lite Session in the debugger at any one time. You may run an EZ-KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ-KIT Lite session.

  • Page 25: Table 3-5 Memory Map

    SDRAM. In this case seg_dmda MUST be located in internal memory. This is caused by a problem with the interrupt handlers in libc.dlb. A correction will be posted to the Analog Devices FTP site.

  • Page 26: Table 3-6 Available Memory Locations On The Ez-Kit Lite

    Table 3-6 shows currently used and available memory locations on the EZ-KIT Lite board. The user may not change these locations in their programs. Table 3-6 Available Memory Locations on the EZ-KIT Lite Memory Range Availability 0x00008000 - 0x0000801F Interrupt Vectors - user (48-bit) 0x00008020 - 0x00008023 IRQ0 vector (reserved by monitor and not overwritten on any .dxe load)

  • Page 27: Using The Ad1819A Soundport Codec As The Analog Front End

    EPROM, or to test AD1819 functionality in a new custom-based 21065L design. For detailed AD1819 and SHARC interface information and example source that demon- strates this second method, contact Analog Devices DSP hotline or search our web site for the following document: Interfacing The ADSP-21065L SHARC DSP to the AD1819a 'AC- 97' SoundPort codec.
  • Page 28 After the SLOT16 bit is set, all subsequent packets are standardized to 16 bits. Once the data is aligned, the EPROM's monitor POST routine then writes and verifies three patterns to an internal register in the codec. If all three writes are verified, the codec connection is verified.
  • Page 29 ADSP-21065L EZ-KIT Lite Monitor Kernel Codec Transfer Scheme Figure 3-1 3.3.3.2.1 DSP/Codec Transmit Sequence 1. The SPORT1 transmit DMA empties the transmit buffer, a SPORT1 transmit interrupt occurs. 2. If the variable Tx Request > 0, then the interrupt loads the data from the User Tx Buffer into the Tx Buffer;...
  • Page 30 3.3.3.3 RS-232 Monitor Codec Memory Map To use the monitor's codec variables, examine the buffers.asm and .ldf files provided with the demos. These two files provide access to the necessary variables by overlapping the locations of the variables. The RS-232 Monitor Program was complied and linked to place the following user variables and buffers to communicated to the codec in the following memory locations: 0x030FFF00 - 0x030FFF05...
  • Page 31 .var _user_tx_buf[6]; .var _user_tx_ready; .var _user_rx_buf[6]; .var _user_rx_ready; .ENDSEG; Note that these variables have a leading underscore to make them C-compatible. If writing in assembly code, include the following segment within the data variable declaration section in the same assembly codec file as the DSP code: .SEGMENT/DM seg_bnk3;...

  • Page 32: Dsp Programming Of The Ad1819 Indexed Control Registers

    21065L EZ-KIT Lite C and assembly programs, the user can inspect the source files for the EZ-KIT Lite audio demos. 3.3.4 DSP Programming of the AD1819 Indexed Control Registers The monitor program provides a setup routine for the AD1819. Table 3-7 shows the registers used by the DSP and their state after reset.

  • Page 33: Demonstration Programs

    4 DEMONSTRATION PROGRAMS 4.1 Overview This chapter describes loading and running the demonstration programs supplied with the ADSP-21065L EZ-KIT Lite board. The demos are designed to run on the VisualDSP++ Debugger which is supplied on the CD that shipped with this product. For detailed information on debugger features and operation, see the VisualDSP++ Debugger Guide &...

  • Page 34: Debugger Operation With The Adsp-21065L Ez-Kit Lite

    The initialization completes and the disassembly window opens. The code in the disassembly window is the EZ-KIT Lite monitor program. 4.3 Debugger Operation with the ADSP-21065L EZ-KIT Lite The VisualDSP++ Debugger Guide & Reference and the Debugger Tutorial (for ADSP-2106x Family DSPs) contains most of the information you need to operate the VisualDSP++ Debugger with your EZ-KIT Lite evaluation board.

  • Page 35: Registers And Memory

    To load a program, use the following procedure: From the File menu, select Load. The Open a Processor Program dialog appears. Navigate to the folder where the DSP executable file resides. The demos that are supplied with the EZ-KIT Lite are located in C:\Program Files\Analog Device\VisualDSP++\21k\EZ- KITs\21065L\demos folder.

  • Page 36: Resetting The Ez-Kit Lite Board

    4.3.4 Resetting the EZ-KIT Lite Board The EZ-KIT Lite board can be reset with the push button switch on the board or with the Debug - > Reset command in the debugger menu bar. Both resets, clear and reset the chips memory and debug information so there will be a need to reload any programs that were running.
  • Page 37 • User must run any program that uses this code from when the function count_start(); starts, to at least as far as the function count_end returns without halting or stepping to obtain an accurate cycle count. #include "bmtools.h" int clock_start, clock count; clock_start = count_start();...

  • Page 38: Demonstration Programs

    • Do not run more than one ADSP-21065L EZ-KIT Lite Session in the debugger at any one time. User may run an EZ-KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ-KIT Lite session.

  • Page 39: Primes.dxe

    4.5.5 Primes.dxe The primes demo program calculates the first 20 prime numbers staring with the number 3 and sends them to the output window. The printf function is used in this demo. • This demo maps seg_dmda into SDRAM. Therefore, any added interrupts other then the codec’s interrupt handler, fail.

  • Page 40: Working With Ez-Kit Lite Hardware

    5 WORKING WITH EZ-KIT LITE HARDWARE 5.1 Overview This chapter discusses hardware design issues on the ADSP-21065L EZ-KIT Lite board. The following topics are covered: • Power Supplies • EPROM Operation • UART • EMAFE The EZ-KIT Lite board schematics are available as an insert at the end of this manual.

  • Page 41: Board Layout

    5.3 Board Layout Figure 5-2 shows the layout of the EZ-KIT Lite board. This figure highlights the locations of the major components and connectors. Each of these major components is described in the following sections. Figure 5-2 EZ-KIT LITE Layout 5.3.1 Boot EPROM The boot EPROM provides up to 1M x 8 bits of program storage that can be loaded by the ADSP- 21065L when it is programmed to boot from EPROM.

  • Page 42: User Push-Button Switches

    5.3.2 User Push-Button Switches For user input/control, there are eight push-button switches on the EZ-KIT Lite board: RESET, FLAG 0-3 , and IRQ 0-2 . • The RESET switch lets you initiate a power-on reset to the DSP. If the user loses contact between the EZ-KIT Lite board and the PC while running programs, use the RESET button to restore communication.

  • Page 43: Power Connector

    The minimum supply voltage for the ADSP-21065L is 3.0V. An ADM708T is used to monitor the supply voltage and holds the processor in reset if the power supply’s voltage is below 3.08V. The board hardware may also be reset via the push button that is connected to this part. For more information, see “User Push-button Switches”...

  • Page 44: Ad1819 Connections

    5.4.5 EMAFE Interface Connector WARNING: Using the EMAFE interface connector to connect to a MAFE board can damage the ADSP-21065L EZ-KIT Lite, the MAFE, or both. Enhanced Modular Analog Front End (EMAFE) connector provides a standard interface for connecting analog input/output daughter boards. The connector has 96 female pins arranged in three rows of 32 pins on a right angle connector.

  • Page 45: Jumpers

    The proper power up sequence is: 1. JTAG Emulator 2. ADSP-21065L EZ-KIT Lite board To remove power, reverse the order. Figure 5-3 JTAG Connector With Jumpers Installed Figure 5-3 shows the locations of the configuration jumpers on the EZ-KIT Lite board and which pin on the jumpers is the GND pin.

  • Page 46: Eprom Size Selection Jumpers

    5.5.2 EPROM Size Selection Jumpers The EZ-KIT Lite supports 128K x 8, 256K x 8, 512K x 8, and 1M x 8 EPROMs, each of which is selectable through jumpers JP4 and JP5. The EPROM socket is originally populated with a 256K x 8 EPROM. If a different EPROM is used, JP4 and JP5 should be adjusted to accommodate the different size.

  • Page 47: Eprom Operation

    5.5.3.1 Line In Selection Jumpers The EZ-KIT Lite uses a single stereo phone jack for line in and the microphone. JP1 and JP2 are use to select between the two functions. The valid settings for these jumpers are shown in Table 5-6. Table 5-6 Line In Selection Description Microphone In...

  • Page 48: Designers Note

    EPROM addressing differs, depending on the silicon revision of the ADSP-21065L on your EZ- KIT Lite board. For revision 0.1 silicon, EPROM addressing begins at address 0x020000. For revision 0.2 and greater, addressing begins at address 0x000000 (i.e. you can use all memory space, see Figure 5-4).

  • Page 49: Emafe

    5.8 EMAFE The indexed addressing required by the EMAFE interface is implemented through the CPLD. The CPLD controls the loading of the address, as well as the data direction of the data bus. As with the UART, the address is only partially decoded. The aliasing seen with the UART also exists with the EMAFE interface in the MS1 address space.

  • Page 50: Timing Diagrams

    Table 5-8 SDRAM pin connections Type Description I/O/Z SDRAM Column Address Select pin. Connect to SDRAM’s CAS buffer pin. SDRAM Data Mask pin. Connect to SDRAM’s DQM buffer pin. The processor drives this pin high during reset, until SDRAM is started. Memory select lines of external memory bank configured for SDRAM.
  • Page 51 Figure 5-6 EMAFE Write Cycle Timing Diagram Figure 5-7 EMAFE Read Cycle Timing Parameter Definitions www.BDTIC.com/ADI...
  • Page 52 Figure 5-8 EMAFE Read Cycle Timing Diagram www.BDTIC.com/ADI...

  • Page 53: Expansion Connectors

    6 Expansion Connectors 6.1 Overview The two expansion connectors provide access to the ADSP-21065L’s interface pins. These pins let the user watch data transmissions. In addition, the host interface, interrupt, and pwm_event pins are also available on this connector. Table 6-1 Expansion Connectors Connector 1 (J2) Connector 2 (J4) Name...

  • Page 54: Emafe Expansion

    Signals routed to the EMAFE daughter board from the ADSP-21065L evaluation board are defined below. Please note, Analog Devices does not provide a daughter board, the user must design this board. www.BDTIC.com/ADI...

  • Page 55: Table 6-2 Evaluation Board Power Connections

    Figure 6-1 Physical Layout of ADSP-21065L DSP evaluation board and EMAFE daughter board EMAFE Signal Description: The EMAFE 96 pin connector routes the following signals from the evaluation board to the EMAFE daughter board. • 16 Data lines. • 8 Address lines. •...
  • Page 56 The EMAFE connector provides a standard interface for connecting analog input/output daughter boards. The connector has 96 pins arranged in three rows of 32 pins. The pinout is given in Table 6-3 and a description of each of the pins is listed alphabetically in Tables 6-4 through 6-6. Table 6-3 EMAFE Connector Row A Row B...

  • Page 57: Emafe Connector Interface Signal Descriptions

    6.2.1 EMAFE Connector Interface Signal Descriptions Table 6-4 EMAFE Connector Interface Signal Description Row A NAME DESCRIPTION DGND Digital Ground Not Used VDD2 +3.3 Digital Power Not Used Not Used Parallel Data Bit 0 (BUFFERED ADSP-21065L D16) Parallel Data Bit 2 (BUFFERED ADSP-21065L D18) Parallel Data Bit 4 (BUFFERED ADSP-21065L D20) DGND Digital Ground...
  • Page 58 Table 6-5 EMAFE Connector Interface Signal Description Row B NAME DESCRIPTION DGND Digital Ground VDD1 Digital Power (5V) VDD2 Digital Power (3.3V) Not Used DGND Digital Ground VDD1 Digital Power (5V) Not Used Not Used DGND Digital Ground Not Used Not Used Not Used VDD1...
  • Page 59 Table 6-6 EMAFE Connector Interface Signal Description Row C NAME DESCRIPTION VDD1 Digital Power (5V) Not Used Not Used DGND Digital Ground Not Used Parallel Data Bit 1 (BUFFERED ADSP-21065L D17) Parallel Data Bit 3 (BUFFERED ADSP-21065L D19) Parallel Data Bit 5 (BUFFERED ADSP-21065L D21) DGND Digital Ground Parallel Data Bit 7 (BUFFERED ADSP-21065L D23)

  • Page 60: Reference

    9600, 19200, 38400, 57600, and 115200. The default rate is 115200. (NOTE: Using a baud rate of 9600 causes the ADSP-21065L EZ-KIT Lite to operate very slowly and can also cause it to hang.) Selects a PC communications port for the ADSP-21065L EZ-KIT Lite board.
  • Page 61 To change the baud rate and COM port should follow these instructions: 1. Bring up the VisualDSP++ Configurator from the Windows Start menu. Click Start->Run, then type Icecfg. Figure 7-2 VisualDSP++ Configurator www.BDTIC.com/ADI...

  • Page 62: Codec

    2. In the Platform Templates box, high light the ADSP-21065L EZ-KIT Lite via COM port, click Copy button. Figure 7-3 will appear Figure 7-3 Platform Properties 3. Click the Baud Rate and COM Port drop-down list to change the settings.
  • Page 63 Figure 7-2 Sample Rate Dialog Source — Choose Microphone or Line In Figure 7-3 Source Setting Gain Select — Select a gain from 0.0 to 22.5 in 1.5 increments www.BDTIC.com/ADI...

  • Page 64: Demo Menu Commands

    7.3 Demo Menu Commands The Demo menu has one command–Demo Control. This command opens a dialog box that lets the user change several operating functions of the FFT and BP demos. Figure 7-3 shows the dialog box that accompanies the FFT demo. Select the Demo Control command for a demo which has no dialogs, an error message that says “This demo does not require user input”...
  • Page 65 Figure 7-5 Bandpass Demo Controls Dialog The dialog fields for the Bandpass demo are as follows: Input Source — Select input from the AD1819, or noise from the DSP. Filter Range — Change the filter applied to the demo. www.BDTIC.com/ADI...

  • Page 66: Appendix A Restrictions & Cpld Code Listing

    11. Do not run more than one ADSP-21065L EZ-KIT Lite session in the debugger at any one time. You may run an EZ-KIT Lite session and a simulator or ICE session at the same time or you can open two debugger interfaces to run more than one EZ-KIT Lite session.
  • Page 67 48000 Hz." The default sample rate is 48000. Do NOT change the sample from this setting. If you need to change sample rates for your program, you will need to write your own CODEC driver. Information on doing this is provided in Chapter 3 of the ADSP-21065L EZ-KIT Lite Evaluation System Manual.
  • Page 68 Listing A CPLD File -- ******************************************************************** -- ** Copyright(c) 1998 Analog Devices, Inc. All Rights Reserved -- ******************************************************************** -- ** Revision History -- ** ---------------- -- ** 05/26/98 Original -- ** 05/27/98 inverted ack output to ack_bar -- ** Allows addition of open collector buffer to be added -- ** 05/29/98 Changed address of UART -- ** 08/15/98 Locked pins to prevent changes on next rev.s...
  • Page 69 bms_bar : in std_logic; -- Wait (EPROM) input u_en_bar, u_rd_bar, u_wr_bar : out std_logic; -- UART Outputs : out std_logic; -- to DSP e_cs_bar, e_rd_bar, e_wr_bar, e_addr : out std_logic; -- EMAFE Outputs codec_rst_bar : out std_logic); -- CODEC Reset attribute pin_avoid of interface:entity is "1 13 21 33";...
  • Page 70 variable cs : std_logic; begin rd := not rd_bar; wr := not wr_bar; cs := not cs_bar; case present_state is when IDLE => u_ack <= '1'; u_ack_v <= '0'; if ((cs = '1') AND ((rd OR wr) = '1') AND (std_match(addr, "001-"))) then -- Proceed only if next_state <= CS1;...
  • Page 71 when ENDW1 => u_ack <= '0'; u_ack_v <= '1'; next_state <= ENDW2; -- Continue Write Cycle when ENDW2 => u_ack <= '0'; u_ack_v <= '1'; next_state <= ENDW3; -- Continue Write Cycle when ENDW3 => u_ack <= '0'; u_ack_v <= '1'; next_state <= ENDW4;...
  • Page 72 "100" when WR2, "100" when WR3, "100" when WR4, "101" when WR_D1, "111" when ENDW1, "111" when ENDW2, "111" when ENDW3, "111" when ENDW4, "101" when CS3, "101" when CS4, "101" when CS5, "101" when CS6, "001" when RD1, "001" when RD2, "001"...
  • Page 73 e_rd_bar <= rd_bar; e_wr_bar <= wr_bar; e_cs_bar <= '0' when ((addr = "0001") AND (cs_bar = '0')) else '1'; e_addr <= '0' when ((addr = "0000") AND (cs_bar = '0')AND (wr_bar = '0')) else '1'; -- ************************************************* Wait Generator for EPROM -- ************************************************* -- Delay the accesses to the EPROM since the DSP will try to -- access it at 30 MHz.
  • Page 74 when WAIT5 => -- Continue Delay w_ack <= '0'; w_ack_v <= '1'; next_wstate <= WAIT6; when WAIT6 => -- Release Delay w_ack <= '1'; w_ack_v <= '1'; next_wstate <= WAIT0; end case; end process wait_state; -- ************************************************* Codec Reset -- ************************************************* cdc_rst: process(clk, addr, cs_bar, reset) variable cdc_cnt: std_logic_vector(4 downto 0);...

  • Page 75: Appendix B Bill Of Materials

    APPENDIX B BILL OF MATERIALS www.BDTIC.com/ADI...
  • Page 76 Item Part Desc Specification Manufacturer/Source:P/N C1, C4, C7, C11, C13, C22, C24, C38, C42, 0.01uF SMT0805 Ceramic, 10%, T&R, 50 V AVX: 08055E103KATMA C60, C62, C74, C75, C91, C92, C95, C105, Panasonic: ECU-1H103KBG C119, C122, C124, C127, C129, C130, C134, C135 C109, C110 22 pF SMT0805...
  • Page 77 C72, C73, C93, C94, C96, C101, C102, C103, C104, C106, C107, C108, C116, C118, C121, C123, C125, C128, C131, C132, C136, C137 C78, C80, C88, C90 1000 pF SMT0805 Z5U, 10%, 50 V Digikey: PCC102BNCT-ND C83, C84 0.33 uF SMT3216 Tantalum, 20%, 35 V Digikey: PCS6334CT-ND Panasonic: ECS-T1VY334R...
  • Page 78 Q1, Q2 PMOS FET TO-263AB P-channel MOSFET, 60W, - Fairchild: NDB6020P 24A, -20V R1, R2, R3, R4 39 Ohm SMT0805 Thick Film, 5%, 1/8 W Digi-Key: P39ACT-ND Panasonic: ERJ-6GEY/J390 R11, R13, R16, R18, R28, R30, R33, R46 100 Ohm SMT0805 Thick Film, 5%, 1/10 W Digi-Key: P100ACT-ND Panasonic: ERJ-6GEYJ101...
  • Page 79 3-State out puts, 5V- Motorola: MC74LCX574DT Tolerant, +/-24 mA, 1.5-8.5 ns, 3.3 V SoundPort 48-pin TQFP AC ‘97 Compliant, 5.0V Analog Devices: AD1819A JST Codec 74LCX125 TSSOP-14 Quad bus buffers w/ 3-state Fairchild: 74LCX125MTC outputs, w/ Bus Hold, 5V- Motorola: MC74LCX125DT Tolerant, +/-24 mA, 1.5-6.0 ns,...
  • Page 80 TSSOP-14 Schmitt Trigger Inverter, 5V- Fairchild: 74LCX14MTC Tolerant, 3.3 V Toshiba: 74LCX14FT ADM232A Narrow SOIC-16 RS232 Driver/Receiver, 2 Tx / Analog Devices: ADM232AARN 2 Rx, 5 V PC16550DV PLCC-44 UART, w/ FIFOs, 1.5M baud, National Semi: PC16550D 74LPT245 SOP-20 Octal Bus Transceiver w/ Bus...

  • Page 81: Appendix C Schematics

    APPENDIX C SCHEMATICS NOTE: TRST is incorrectly documented in the schematic as active high. It should be active low (!TRST). Also REDY is incorrectly documented in the schematic as active low (!REDY). It should be active high active. www.BDTIC.com/ADI...

  • Page 82: Index

    +3.3Vcc +3.3Vcc +3.3Vcc Host Boot +3.3Vcc +3.3Vcc +3.3Vcc EPROM Boot Initially JP6 = 2-3 SDCLK0 SJP6 SJP7 SJP8 BTDI SDCKE SBTS# TRST BTRST SDWE# CAS# Jumper3 Shunt Shunt Shunt BTCK RAS# SDA10 BTMS +3.3Vcc When not used jumper pins CLKIN 7 - 8 9 - 10 EZ-ICE...
  • Page 83 EMAFE_CS# 1DIR EMAFE_RD# 2DIR D[0..15] Bypass Caps for +3.3Vcc MD10 MD11 +3.3Vcc MD12 EMAFE_ADDR MD13 Bypass Caps for MD14 MD15 C105 C106 +3.3Vcc Vcc1 GND1 Vcc2 GND2 Vcc3 GND3 Vcc4 GND4 GND5 GND6 GND7 +3.3Vcc GND8 74LVTH16245A 74LVT574 +3.3Vcc The ADSP-21065L must be programmed to use a Hold Time Cycle on MS1 U11F...
  • Page 84 A[0..19] DQ10 DQ11 SDA10 SDA10 DQ12 DQ13 Non-schematic J5 and J4 should be adjusted MS3# MS3# DQ14 Component depending on size of EPROM. RAS# DQ15 Sock et for EPROM CAS# SDWE# Rev.s 0.0 and 0.1 of the ADSP-21065L begin DQMH 128K x 8, 256K x 8 accessing the EPROM at 0x020000.
  • Page 85 +3.3Vcc +3.3Vcc +5Vcc +3.3Vcc U21A DSP_CLK Ferrite Bead 39 Ohm 39 Ohm 74LCX14 30.0000MHz U21B PLD_CLK 39 Ohm 74LCX14 +3.3Vcc C8 is used to minimize U21C +5VA noise on the board EXT_CLK where 5Vcc crosses the 39 Ohm +3.3Vcc plane. +5Vcc 74LCX14 U21D...
  • Page 86 EMAFE UART-CPLD D[0..15] A[0..5] EMAFE_WR# EMAFE_WR# D[0..7] EMAFE_RD# EMAFE_RD# EMAFE_CS# EMAFE_CS# EMAFE_ADDR EMAFE_ADDR CODEC_RST# PROM_CS* MS1# PLD_CLK PLD_CLK IRQ0# UART-CPLD IRQ1# MFLAG TFS0 DT0A DT0B TXCLK0 RFS0 DR0A DR0B RXCLK0 TFS1 Codec DT1A DT1B CODEC_RST# A[0..23] A[0..23] IRQ0# IRQ0# A[0..23] TXCLK1 D[0..31] D[0..31]...
  • Page 87 +5Vcc A[0..5] BAUDOUT D[0..7] Ferrite Bead RCLK +5Vcc UART_RD# UART_EN# 0.1uF OUT1 Ferrite Bead OUT2 T1_IN T1_OUT RTS# T2_IN T2_OUT CTS# R1_OUT R1_IN +3.3Vcc Ferrite Bead SOUT Female DB9 UART_RD# R2_OUT R2_IN 74LPT245A UART_WR# ADM232A INTR +5Vcc Cap added to reduce TXRDY 74F06 Ferrite Bead...
  • Page 88 D[0..31] +3.3Vcc General purpose LEDs +3.3Vcc +3.3Vcc +3.3Vcc +3.3Vcc +3.3Vcc +3.3Vcc FLAG[0..3] FLAG0 100 Ohm 74LCX14 PUSHB UTTON1 Green Green Green Green Green Green 11 12 +3.3Vcc 13 14 15 16 17 18 19 20 21 22 U11A FLAG[4..9] 23 24 FLAG4 25 26 FLAG1...
  • Page 89 +3.3Vcc Bypass Caps for Line In Circuit +5Vcc +5Vcc +5VA +5VA CODEC_ON# C100 Place C82, C85, R39, and R40 as SJP3 10uF 10uF 10uF 10uF JP3 = 1-2 if C101 C102 C103 C104 close as possible EMAFE Interface to J8 uses SPORT1 +3.3Vcc Shunt...
  • Page 90 INDEX starting ............... 32 Default Settings on the EZ-LAB ......15 ADSP-21065L Demo menu commands ......... 63 interrupts............26 Demo programs Analog Front End overview ............32 AD1819 ............. 26 Demonstration programs bandpass filter............ 37 Blink ..............38 FFT ..............37 Bandpass demo dialog ...........
  • Page 91 EMAFE ............. 43 Resetting the board ..........19 EPROM ............. 40 power supplies ........... 41 SDRAM............. 48 SDRAM..............48 UART ..............47 SDRAM data mask........See DQM Hardware installation..........13 SDRAM interface data transfer rate ..........48 features .............. 48 IMASK register .............

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