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Data Transfer
minimum of 48 cycles over a 16-bit wide external bus (excluding any con-
flicts for data operand fetches). However, with the presence of the
instruction cache, and assuming that the execution is from external
SDRAM, and that the instructions are on the same SDRAM page, the
number of cycles is reduced to 17 over a 16-bit wide external bus, and
either 15 cycles or 16 cycles over a 32-bit wide bus (depending on whether
instruction 1 begins on an even 32-bit address, or odd 32-bit address).
Thus, the internal cache improves the efficiency of execution from 16-bit
wide external memory by approximately 64.5% for this example.
As might be expected, it is important to remember that the instruc-
tion cache does not play a significant role in improving the
efficiency of strictly linearly executed code from external memory.
Fetching VISA Instructions From External Memory
The SHARC processors support fetching instructions from external
SDRAM or DDR2 memory. These instructions may be stored either as
traditional 48-bit SHARC ISA instructions, or as VISA instructions.
There is an overhead incurred when fetching data in general directly from
external memory owing to inherent latencies and overheads associated
with accessing SDRAM/DDR2 memory. Additionally, there are latencies
involved with accessing non-sequential VISA instructions from external
memory because of the width of the external SDRAM/DDR2 data bus
(instructions have to be fetched as 16-bit units).
In VISA operation, the sequencer fetches 3 x 16-bit of data which decodes
in one, two or three instructions. For more information on VISA opera-
tion refer to the SHARC Processor Programming Reference.
Just as the same physical internal memory on the processors can be
accessed and addressed in many different ways, the external memory space
can also be viewed either as logical or physical addresses. To support VISA
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ADSP-214xx SHARC Processor Hardware Reference
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