Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 890

Peripheral Registers
15
EXTTXFR_DONE_MSK
External Transfer Done Mask
LPIT_MSK
Invalid Transmit Interrupt Mask
DMACH_IRPT_MSK
DMA Channel Interrupt Mask
LRRQ_MSK
Link Port Receive Request Mask
LTRQ_MSK
Link Port Transmit Request Mask
Figure A-28. LCTLx Registers
Table A-33. LCTLx Register Bit Descriptions (RW)
Bit Name
0 LEN
1 LDEN
2 LCHEN
3 LTRAN
6–4 Reserved
7 LP_BHD
8 LTRQ_MSK
A-64
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14 13 12 11 10 9 8 7
Description
Link Buffer Enable. Enables (if set, =1) or disables (if cleared, =0)
link buffer x (LBUFx). When the processor disables the buffer (LxEN
transitions from high to low), the processor clears the corresponding
LxSTAT and LxRERR bits.
Link Buffer DMA Enable. Enables (if set, =1) or disables (if cleared,
= 0) DMA transfers link buffer x (LBUFx).
Link Buffer DMA Chaining Enable. Enables (if set, =1) or disables
(if cleared, =0) DMA chaining link buffer x (LBUFx).
Link Buffer Transfer Direction. This bit selects the transfer direction
(transmit if set, =1) (receive if cleared, = 0) for link buffer x (LBUFx).
Buffer Hang Disable.
0 = Core stalls when read from empty receive or write to full transmit
buffer attempted
1 = Prevents a core hang.
Link Port Transmit Request Mask.
0 = Mask
1 = Unmask
ADSP-214xx SHARC Processor Hardware Reference
6 5 4 3 2 1 0
LEN
Link Buffer Enable
LDEN
Link Buffer DMA Enable
LCHEN
Link Buffer DMA Chaining
Enable
LTRAN
Link Buffer Transfer
Direction
LP_BHD
Buffer Hang Disable