Idle State; Processing State; Write State - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

Resetting via a logic low to the
ing the
FFT_RST
a logic high to the
the next clock cycle.

Idle State

This mode is used to program the accelerator's control registers. Setting
the and
FFT_EN
from idle to reading.
Read State
In this state the module reads data and coefficients, but counts the num-
ber of read data only. This is because for successive FFT calculations the
coefficient need not be read again—only the next set of data has to be
read. When a specified number of data words are read, the state automati-
cally moves to processing.

Processing State

In this mode the module computes FFT ping-pong stages in memory.
Once this is done, the state automatically moves to the write state.

Write State

In this mode all the computed data is written out to internal memory. The
state then automatically changes to either idle or read, depending on the
way the block is configured using the repeat function (
register). If the
FFTCTL2
state, if cleared, the block moves to the idle state. The
when programs need to continuously perform an FFT on input data with-
out core intervention.
ADSP-214xx SHARC Processor Hardware Reference
www.BDTIC.com/ADI
RESET
bit. Once the processor is brought out of reset by applying
pin, the FFT module goes into the idle state in
RESET
bits in the
FFT_START
bit is set, the block moves to the read
FFT_RPT
FFT/FIR/IIR Hardware Modules
pin resets all registers, thereby clear-
register moves the state
FFTCTL1
FFT_RPT
FFT_RPT
bit in the
bit is useful
6-7