Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 180

DDR2 DRAM Controller (ADSP-2146x)
and falling edges of the
DDR2 DLL using a delayed
degrees for the positive edge data and by approximately 90 degrees for the
negative edge data. These delays are precisely generated using the internal
DDR2 DLL circuit.
The captured data is sent out, corresponding to the data launched by the
DRAM with the positive edge and negative edge of
Both data buses are internally retimed such that they can be captured
directly by the controller on the positive edge of
the arbitrary phase relation that may exist between
. During initial operation (external bank calibration), the DLL
DDR2_DQS
determines the phase difference between the
retimes the data captured accordingly.
During a DRAM write, the DDR2 controller performs the multiplexing
of positive and negative edge data. This in turn is driven onto
data when the write path in the memory I/O buffers is activated. The cor-
responding write
after a phase shift of 90 degrees (controlled by the DLL).
The configuration is programmed in the
controller can hold off the processor core or DMA controller with an
internally connected acknowledge signal, as controlled by refresh, or page
miss latency overhead. A programmable refresh counter is provided which
generates background auto-refresh cycles at the required refresh rate based
on the clock frequency used. The refresh counter period is specified using
the field in the DDR2 refresh rate control register
RDIV
Control Register (DDR2RRC)" on page
The DDR2C uses burst length 4 (BL = 4) for read and write operations.
This requires the DDR2C to post only the first read or write address on
the bus, all subsequent sequential address are posted by the DDR2 inter-
nal burst counter.
3-50
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signal. The read data is captured by the
DDR2_DQS
that is phase shifted by approximately 90
DQS
is also driven through the memory I/O, but
DDR2_DQS
ADSP-214xx SHARC Processor Hardware Reference
DDR2_DQS
, irrespective of
DDR2_CLK
DDR2_CLK
and
DDR2_CLK DDR2_DQS
registers. The DDR2
DDR2CTL5-0
("Refresh Rate
A-36).
respectively.
and the
and
as write
DQ