Analog Devices SHARC ADSP-214 Series Hardware Reference Manual page 798

Processor Booting
Since the SPI host initiates the transfers, a handshake between master and
slave is required for synchronization. One possible solution is to use the
slave's
SPI_MISO_O
slave transmits zeros or ones to the master. Another solution is to connect
this signal to the master's flag input to generate an interrupt for the same
purpose.
Table 23-9. SPICTL Slave Boot Settings (0x4D22)
Bit Setting
SPIEN Set (= 1)
SPIMS Cleared (= 0)
MSBF Cleared (= 0)
WL 10, 32-bit SPI
DMISO Set (= 1) MISO
SENDZ Cleared (= 0)
SPIRCV Set (= 1)
CLKPL Set (= 1)
CPHASE Set (= 1)
The SPI DMA channel is used when downloading the boot kernel infor-
mation to the processor. At reset, the DMA parameter registers are
initialized to the values listed in
Table 23-10. Parameter Initialization for SPI Slave Boot
Parameter Register
SPIDMAC
IISPI
IMSPI
CSPI
23-16
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signal as handshake signal. If a pause is required, the
Comment
SPI enabled
Slave device
LSB first
Receive shift register word length
MISO disabled
Send last word
Receive DMA enabled
Active low SPI clock
Toggle SPICLK at the beginning of the first bit
Table
Initialization Value
0x0000 0007
IVT_START_ADDR
0x1
0x180
ADSP-214xx SHARC Processor Hardware Reference
23-10.
Comment
Enable receive, interrupt on completion
Start of block 0
32-bit data transfers
×
384 32-bit transfers